DSP ASIC Verification Engineer - Optical Transmission Systems

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Ciena’s WaveLogic family of products is a core component of optical transmission solutions, enabling high-performance telecommunications networks globally. This role contributes to the validation and quality of these products through rigorous digital verification. The position plays a critical role in ensuring reliable functionality across complex subsystems and architectural components.

How you will make an impact:

• Design and execute verification activities for architectural functional blocks within the WaveLogic product family

• Analyse architecture and functional requirement specifications and collaborate with systems engineers and architects

• Develop and implement validation strategies using simulation, formal methods, and coverage techniques

• Create and integrate verification environments including test benches, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C

• Define and implement functional coverage models and contribute to verification planning

• Perform coverage-driven verification, analyse regression results, and debug failures in collaboration with design engineers

• Report verification progress, issues, and status updates on a regular basis.

The must haves:

• Education: Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or other applicable scientific discipline

• Experience: 3+ years of experience in digital design verification of complex circuits

• Application of SV-UVM, SVA, and C++ in verification environments

• Creation of verification plans based on functional and architectural specifications

• Development of verification environments using SV-UVM and C++

• Application of metric-driven verification methods including functional coverage

• Utilization of EDA verification tools and flows from major vendors.

• Candidates should have good English communication skills, solid problem-solving capabilities, and demonstrate a high level of motivation with the ability to work independently.

Nice to haves:

• Experience: Experience with formal verification methods

• Experience: Experience with coherent DSP architectures

• Experience: Experience with standards and protocols such as OTN/FlexO/B100G and Ethernet (100GE+)

• Experience: Experience using GIT for source code management and revision tracking

• Experience: Experience using Jira for schedule planning, assignment tracking, and bug reporting

• Application of programming languages such as Python, Make, Bash, C, and C++

• Basic communication skills in German.

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Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

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