Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips

Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips

Duration : 6 months

Location : Eindhoven, Netherlands (hybrid)

Background and Motivation

Automotive PHY devices expose their configuration and status registers over the Serial Management Interface (SMI), a two-wire serial bus (MDC / MDIO) defined by IEEE 802.3 Clause 22/45.

In the current implementation, the SMI link carries no inherent data-integrity protection: there is no parity bit, no CRC, and no acknowledgment mechanism in the baseline protocol.

In a harsh automotive EMC environment, single-bit upsets on the MDIO bus can silently corrupt a register write, causing a PHY to enter an incorrect operating mode without any indication to the host.

To guard against this, the software driver currently performs write-then-read-back verification and double-read redundancy checks.

These software workarounds increase bus utilization, add latency to every configuration transaction, and consume CPU cycles in a safety-critical context.

This internship investigates and prototypes hardware-based robustness mechanisms that can detect or correct bit errors on the SMI bus, or within the on-chip register file, transparently to the software layer.

What You Will Learn

• SMI / MDIO protocol internals at silicon level
• Digital RTL design in SystemVerilog (FSMs, protocol wrappers, register-file architectures)
• Fault-injection verification and coverage-driven testbench methodology
• Professional chip-design workflow: code review, EDA tools

Profile

• Final-year BSc in Electrical Engineering, Microelectronics, Embedded Systems, or Computer Engineering
• Basic digital logic design knowledge; familiarity with at least one HDL (Verilog / SystemVerilog / VHDL)
• Analytical, structured approach to trade-off problems; reads technical English comfortably

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