Senior/Staff Process Engineer (Wafer Bumping/Fan-Out)

Core Responsibilities

1. Lead the process development and technical support of the wafer bumping, and/or Fan-Out process for silicon photonic chip wafers, with OSAT or at internal line.

2. Process Pathfinding & Integration: Design and optimize early-stage process flows for wafer bumping, thin-film sputtering, lithography, electroplating, and ball drop execution. DOE to characterize process window and margin.

3. Material Characterization & Selection: Evaluate and qualify new manufacturing raw materials, including dielectric photoresists, plating chemistries, underfills, and solder alloys.

4. Design and execute DOE plans to characterize thermal and mechanical stress. Lead reliability validations including Temperature Cycling Test (TCT), Unbiased Highly Accelerated Stress Test (HAST) and High-Temperature Storage (HTS).

5. Failure Analysis & Debug: Own the root-cause diagnostics of structural failure modes unique to WLCSP (e.g., RDL cracking, bridging ball bridging, bump missing, delamination, or wafer warpage). Utilize specialized analytics instrumentation including SEM, CSAM, and physical cross-sectioning. Conduct root cause analysis and formulate improvement solutions.

6. Optimize key bumping process parameters including wafer cleaning, UBM sputtering, solder ball plating, reflow and bump inspection to improve bump uniformity and yield.

7. Manage incoming wafer quality control, establish SPC control plans and monitor process variation to ensure long-term process stability

8. Compile process SOP, WI, process failure reports and engineering change documents; support NPI new product introduction and process verification.

Key Requirements & Qualifications

• Education: A bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.

• Experience: 5+years of hands-on wafer bumping or Fan-out process integration or development experience, at OSAT or IDM internal advanced packaging line. Process exposure/experience on interposer, 2.5D/3D, chip on wafers on substrate, will be an added advantage.

• Technical Knowledge:

• Deep practical understanding and hands-on experience of photolithography, wet etching, chemical vapor deposition (CVD), and physical vapor deposition (PVD), moulding process adapted for backend bump fabrication.

• Comprehensive command of finite element simulation principles regarding warpage, thermal dissipation, and structural mechanical integrity.

• Solid working expertise with industry validation methodologies including FMEA, SPC controls, and structured 8D problem-solving tools.

• Software Tools: High proficiency with robust analytical platforms like JMP, Minitab, or Python.